Many communications and processing devices include circuitry that operates according to different required clock input signals. A viable choice would be a clock tree generating all the required clock frequencies from one single input reference clock. Typically this can be realized by feeding the reference clock to a PLL to create and intermediate high frequency clock signal followed by one or more frequency dividers dividing the high frequency clock to generate lower frequency clock signals for use by the individual circuits. Some frequency divider applications require an integer relationship between the input frequency and the output frequency, where the frequency divider circuit is a counter providing a divider ratio of 1/K, where K is an integer. However, new applications often require one or more output frequencies that do not have an integer relationship to the input clock frequency. Certain fractional divider architectures provide integer fraction output frequencies, such as ⅔, or generally J/K where J and K are small integers to allow for practical intermediate frequencies. Many applications, moreover, require clock tree solutions where several output clocks are generated from one single reference clock, with no restriction on the frequency of the output clock signals. For instance, certain applications involve different data interfaces residing in a single device, each requiring a different clock frequency. In addition, many clock divider applications require output clock signals of high quality with very low level of phase noise, low time domain jitter and control of unwanted spurs, in addition to low power consumption and complexity in terms of occupied area.